1. Field of the Invention
The present invention relates to a semiconductor device and a method for making the same, and more particularly to isolate a device region and device isolation region by forming a device isolation layer on a semiconductor substrate.
2. Description of the Related Art
Conventionally, a device isolation method known as selective oxidation has been employed to provide the electrical isolation necessary between the various device elements within the semiconductor integrated circuits.
The following is one well known example of a device isolation method employing the conventional art of selective oxidation. Firstly, oxidation and anti-oxidation layers are formed on the semiconductor substrate. Then, this anti-oxidation layer is selectively etched. Next, impurity doping known as the channel stopper is applied to this etched area in order to control the parasitic threshold voltage which will occur in the device isolation region. After this, the device isolation layer is formed by thermal oxidation, and in this way electrical isolation between the various device elements is achieved.
A detailed explanation of the above selective oxidation method for device isolation is given by FIG. 13. This processes involved in this device isolation method employing the conventional art of selective oxidation are described below.
(a) A thin oxidation layer 2 is formed on the semiconductor substrate 1.
(b) Next, an anti-oxidation layer 3 made from silicon nitride is deposited on the oxidation layer 2 by a process such as chemical vapor deposition (CVD).
(c) After this, an arbitrary portion of the anti-oxidation layer 3 is masked with a photoresist mask 4, and the region of the anti-oxidation layer which is not covered by the mask is removed by dry etching.
(d) Then, some impurities 5 having the same polarity as the semiconductor substrate are introduced via ion implantation.
(e) After this, isolation between the device region 10 and the device isolation region 14 is attained by growing a device isolation layer 6 on the semiconductor substrate through thermal oxidation.
(f) Lastly, the remainder of the anti-oxidation layer is removed.
(g) If a transistor region is formed in the device element region 10, some channel doping impurities 9 are implanted in order to control the threshold voltage for the transistor region, after which a gate 8 is formed.
Now, when the above method of formation of the device isolation layer is employed, regions known as bird's beak regions are formed at both ends of the device isolation layer as shown in FIG. 13. Also, there is an imbalance in the impurity concentration distribution for the border region 12 between the device region 10 and the device isolation region 14. Consequently, generation of bird's beak region 7 and occurrence of the imbalance of the impurity concentration distribution in the border region 12 are the source of the following problems.
(1) The first problem is that the bird's beak region 7 prevents the fine pattern process with the reason as follows.
Usually, the device isolation performance of the device isolation region 14 will improve if the parasitic threshold voltage of that region is increased. In order to increase the parasitic threshold voltage, the impurity concentration of the device isolation region 14 should be increased or the device isolation layer 6 should be made thick. However, as shown in FIG. 13, the device isolation layer 6 at the bird's beak region 7 is thin, so the parasitic threshold voltage at the bird's beak region 7 cannot be sufficiently increased. The device isolation region 14 can therefore not function effectively. The result of this is that the minimum pitch between elements is lengthened by the length of the bird's beak region 7, which is a major obstruction to the fine pattern process.
In particular, in case of LSI or ULSI such as DRAM, SRAM and DSP, reducing the minimum pitch between elements is a general way to get high degree of integration. This means that there are problems, namely, if the minimum pitch between elements is lengthened by the length of the bird's beak region 7, the area of LSI or ULSI will increase by a factor of two. This will increase the device cost and reduce the production yield.
It is well known that, for example, by increasing the ratio between the thicknesses of the anti-oxidation layer 3 and the thin oxidation layer 2, the area of the bird's beak region 7 can be reduced. This produces a new problem such that the stress generated during the growth of the oxidation layer 2 causes crystal defects in the substrate. In addition to this method, there is another high precision engineering method known as the shallow trench isolation. However, this method has many problems because this manufacturing process involves a large number of separate steps and the contents of these steps are quite complicated.
(2) The second problem is that imbalances in the impurity concentration distribution in border region 12 are detrimental to the characteristics of the device. Detriments such as narrow channel effects can be seen in the device characteristics. Moreover, phenomena such as the increase of a leakage current and the reduction of the breakdown voltage in the border region 12 can then be observed. The causes of these phenomena are as follows.
In the conventional method, the photoresist 4 and anti-oxidation layer 3 prevent the impurities 5 to be used as the channel stopper 5 for the device isolation from being introduced into the device region 10. As a result of this, there is an imbalance in the impurity concentration distribution in the border region 12 between the device region 10 and the device isolation region 14 because the impurities 5 are introduced only into the device isolation region 14. In particular, the bird's beak region 7 absorbs fewer impurities because the device isolation layer 6 is thin. This means that more impurities remain in the region below the bird's beak region 7. So the imbalance in the impurity concentration distribution is more aggravated by this. Resultingly, during the thermal oxidation process or the like, some of the remaining impurities may diffuse their way into the device region 10.
If the device region 10 is formed as a transistor region, this diffusion of impurities into the device region 10 profoundly affects the characteristics of the transistor. That is, because an inversion region is hard to be formed in the device region 10 due to the diffused impurities, the transistor threshold voltage is increased. When the transistor width W is narrower, this tendency becomes more noticeable and a phenomenon known as narrow channel effects as shown in FIG. 5 is produced.
Additionally, if the device region 10 is formed as an active region made of impurities which has a polarity opposite to that of the substrate, the following problems will occur. There will be an imbalance in the impurity concentration distribution of the border region 12 and the breakdown voltage in this region will become low. Also, impurities of an another polarity will diffuse into the active region and a leakage current for this region will increase. There will be detrimental effects towards, for example, the device reliability and the product yield.